PCECL308 LOGIC CIRCUIT DESIGN LAB → ASYNCHRONOUS COUNTER

PCECL308 LOGIC CIRCUIT DESIGN LAB

Curriculum

29 Sections
29 Lessons
10 Weeks

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Exp. No.:1 Study of Logic Gates and Realization of Logic Circuits using Basic Gates.
• To study about Logic Gates and verify their truth tables. • To implement the given Boolean function using logic gates in SOP and POS forms.
1
- 1.1
  Basic Gates
Exp. No.:2 Half Adder And Full Adder
To design and realize half adder and full adder and verify the truth table using basic gates and universal gates
1
- 2.1
  HALF ADDER & FULL ADDER
Exp. No.:3 Half Subtractor and Full Subtractor
To design and realize half subtractor and full subtractor and verify the truth table using basic gates and universal gates
1
- 3.1
  Half Subtractor and Full Subtractor
Exp. No.:4 Multiplexer and Demultiplexer
To design and implement mux/demux and encoder/decoder using logic gates
1
- 4.1
  Multiplexer and Demultiplexer
Exp. No.:5 Study of Flip Flops
• To study about flip flops and verify the truth tables of master slave JK, D and T flip Flop using logic gates. • Familiarize with flip flop ICs 7473 (JK flip flop), 7474 (D flip flop) and 7476 (JK flip flop).
1
- 5.1
  Study of Flip Flops
Exp. No.:6 Asynchronous Counters
• To design and realize 3-bit Asynchronous up counter, Asynchronous down counter and 3- bit asynchronous up-down counter. • To design and realize 4-bit up counter. • To design and realize Mod – 6 counter.
1
- 6.1
  Asynchronous Counters
Exp. No.:7 Synchronous Counters
• To design and construct 4-bit synchronous up counter • To design and construct 3 bit up/down counter
1
- 7.1
  Synchronous Counters
Exp. No.:8 Shift Registers
To design and setup shift registers and to study SISO, SIPO, PIPO and PISO using IC7474.
1
- 8.1
  Shift Registers
Exp. No.:9 Ring Counter and Johnson Counter
To design and setup four bit Ring counter and Johnson counter using J K Flip flop
1
- 9.1
  Ring Counter and Johnson Counter
Exp. No.:10 Encoder and Decoder
To design and implement encoder/decoder using logic gates
1
- 10.1
  Encoder and Decoder
Part B – VERILOG
INTRODUCTION
1
- 11.1
  VERILOG EXPERIMENTS
Exp. No.:1 LOGIC GATES
Write a Verilog program for logic gates and universal gates using any type of modelling
1
- 12.1
  LOGIC GATES
Exp. No.:2 HALF ADDER
Write a Verilog program for half adder using data flow and gate level modelling
1
- 13.1
  HALF ADDER
Exp. No.:3 FULL ADDER
Write a Verilog program for full adder using gate level modelling and behavioral level modelling.
1
- 14.1
  FULL ADDER
Exp. No.:4 HALF SUBTRACTOR
Write a verilog code for half subtractor using dataflow and structural modelling.
1
- 15.1
  HALF SUBTRACTOR
Exp. No.:5 FULL SUBTRACTOR
To write a verilog code for full subtractor using behavioural level and structural level modelling.
1
- 16.1
  FULL SUBTRACTOR
Exp. No.: 6 MULTIPLEXER
Write a Verilog program for Multiplexer using gate level and dataflow modelling
1
- 17.1
  MULTIPLEXER
Exp. No.:7 DEMULTIPLEXER
Write a Verilog program for De-multiplexer using gate level and dataflow modelling.
1
- 18.1
  DEMULTIPLEXER
Exp. No.:8 ENCODER
Write a Verilog program for encoder using gate level and dataflow modelling.
1
- 19.1
  ENCODER
Exp. No.:9 DECODER
Write a Verilog program for encoder using gate level and dataflow modelling.
1
- 20.1
  DECODER
Exp. No.:10 FOUR BIT FULL ADDER/PARALLEL ADDER
Write Verilog code for 4-bit full adder / parallel adder using 1 bit full adder using structural level modelling.
1
- 21.1
  FOUR BIT FULL ADDER/PARALLEL ADDER
Exp. No.:11 FULL ADDER USING TWO HALF ADDERS
Write Verilog code for full adder using two half adders using structural level modelling
1
- 22.1
  FULL ADDER USING TWO HALF ADDERS
Exp. No.:12 FLIP FLOPS
Write Verilog code for the following flip flops using behavioural modelling.1. JK flip flop 2. SR flip flop 3. D flip flop 4. T flip flop
1
- 23.1
  FLIP FLOPS
Exp. No.:13 EQUATION SOLVING
Write Verilog code for the equation given below using gate level and data level modelling. 1) y = abc + a’b’c + a’b’c’ + ab’c 2) y = ab + c’ + abc
1
- 24.1
  EQUATION SOLVING
Exp. No.:14 SYNCHRONOUS COUNTER
Write a Verilog program for synchronous up down counter using behavioural level modelling and structural level modelling.
1
- 25.1
  SYNCHRONOUS COUNTER
Exp. No.:15 ASYNCHRONOUS COUNTER
Write a Verilog program for asynchronous up down counter using behavioural level modelling and structural level modelling.
1
- 26.1
  ASYNCHRONOUS COUNTER
Exp. No.:16 RING COUNTER
Write a Verilog program for ring counter using structural level modelling.
1
- 27.1
  RING COUNTER
Exp. No.:17 JOHNSON COUNTER
Write a Verilog program for Johnson counter using structural level modelling
1
- 28.1
  JOHNSON COUNTER
VIVA Questions
Digital Lab viva questions
1
- 29.1
  VIVA

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SYNCHRONOUS COUNTER

PCECL308 LOGIC CIRCUIT DESIGN LAB

Curriculum

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