| Course Code | PCECL308 | CIE Marks | 50 |
| Teaching Hours/Week (L: T:P: R) |
0:0:3:0 |
ESE Marks |
50 |
| Credits | 2 | Exam Hours | 2 Hrs. 30 Min. |
| Prerequisites (if any) | None | Course Type | Lab |
| Expt. No. | Experiments |
| Part A – List of Experiments using digital components (Any Six experiments mandatory) | |
| 1 | Realization of functions using basic and universal gates (SOP and POS forms). |
| 2 | Design and Realization of half/full adder and subtractor using basic gates and universal gates. |
| 3 | 4 bit adder/subtractor and BCD adder using 7483 |
| 4 | Study of Flip Flops : S-R, D, T, JK and Master slave JK FF using NAND gates |
| 5 | Asynchronous Counter : 3 bit up/down counter, Realization of Mod N Counter |
| 6 | Synchronous Counter: Realization of 4-bit up/down counter, Realization of Mod-N counters |
| 7 | Ring counter and Johnson Counter. |
| 8 | Realization of counters using IC’s (7490, 7492, 7493). |
| 9 | Realization of combinational circuits using MUX & DEMUX, using ICs (74150, 74154) |
| 10 | Sequence Generator / Detector |
| Part B – Simulation Experiments (Any Six experiments mandatory)
The experiments shall be conducted using Verilog and implementation using small FPGA |
|
|
1 |
Experiment 1: Realization of Logic Gates and Familiarization of FPGAs |
| (a) Familiarization of a small FPGA board and its ports and interface.
(b) Create the .pcf files for your FPGA board. (c) Familiarization of the basic syntax of verilog Development of verilog modules for basic gates, synthesis and implementation in the above FPGA to verify the truth tables. (e) Verify the universality and non associativity of NAND and NOR gates by uploading the corresponding verilog files to the FPGA boards. |
|
|
2 |
Experiment 2: Adders in Verilog
(a) Development of verilog modules for half adder in any of the 3 modeling styles (b) Development of verilog modules for full adder in structural modeling using half adder. |
|
3 |
Experiment 3: Mux and Demux in Verilog
(a) Development of verilog modules for a 4×1 MUX. (b) Development of verilog modules for a 1×4 DEMUX. |
|
4 |
Experiment 4: Flipflops and counters
(a) Development of verilog modules for SR, JK and D flipflops. (b) Development of verilog modules for a binary decade/Johnson/Ring counters |
|
5 |
Experiment 5. Multiplexer and Logic Implementation in FPGA
(a) Make a gate level design of an 8 : 1 multiplexer, write to FPGA and test its functionality. (b) Use the above module to realize any logic function |
|
6 |
Experiment 6. Flip-Flops and their Conversion in FPGA
(a) Make gate level designs of J-K, J-K master-slave, T and D flip-flops, implement and test them on the FPGA board. (b) Implement and test the conversions such as T to D, D to T, J-K to T and J-K to D |
|
7 |
Experiment 7: Asynchronous and Synchronous Counters in FPGA
(a) Make a design of a 4-bit up down ripple counter using T-flip-flops in the previous experiment, implement and test them on the FPGA board. (b) Make a design of a 4-bit up down synchronous counter using T-flip-lops in the previous experiment, implement and test them on the FPGA board. |
|
8 |
Experiment 8: Universal Shift Register in FPGA
(a) Make a design of a 4-bit universal shift register using D-flip-flops in the previous experiment, implement and test them on the FPGA board. (b) Implement ring and Johnson counters with it. |
|
9 |
Experiment 9. BCD to Seven Segment Decoder in FPGA
(a) Make a gate level design of a seven segment decoder, write to FPGA and test its functionality. (b) Test it with switches and seven segment display. Use ouput ports for connection to the display. |
Course Outcomes (COs)
At the end of the course students should be able to:
| Course Outcome | Bloom’s Knowledge
Level (KL) |
|
| CO1 | Design and demonstrate the functioning of various combinational and
sequential circuits using ICs |
K3 |
| CO2 | Apply an industry compatible hardware description language to implement
digital circuits |
K3 |
| CO3 | Implement digital circuits on FPGA boards and connect external hardware to
the boards |
K3 |
| CO4 | Function effectively as an individual and in a team to accomplish the given
task. |
K2 |
| PO1 | PO2 | PO3 | PO4 | PO5 | PO6 | PO7 | PO8 | PO9 | PO10 | PO11 | PO12 | |
| CO1 | 3 | 3 | 3 | 2 | 3 | 3 | ||||||
| CO2 | 3 | 1 | 1 | 3 | 3 | 3 | 1 | 3 | ||||
| CO3 | 3 | 1 | 1 | 3 | 3 | 3 | 1 | 3 | ||||
| CO4 | 3 | 3 | 3 | 3 | 3 | 3 |
| Text Books | ||||
| Sl. No | Title of the Book | Name of the Author/s | Name of the Publisher | Edition and Year |
| 1 | Verilog HDL Synthesis: A
Practical Primer |
J. Bhasker | B. S. Publications, | 2001 |
| 2 | Fundamentals of Logic Design | Roth C.H | Jaico Publishers. V Ed., 2009 | 5th Edition |
Reference Books
| Sl. No | Title of the Book | Name of the Author/s | Name of the
Publisher |
Edition
and Year |
| 1 | Verilog HDL :A guide to digital design and synthesis |
Palnitkar S. |
Prentice Hall; 2003. |
2nd Edn., |
Curriculum
- 29 Sections
- 29 Lessons
- 10 Weeks
- Exp. No.:1 Study of Logic Gates and Realization of Logic Circuits using Basic Gates.• To study about Logic Gates and verify their truth tables. • To implement the given Boolean function using logic gates in SOP and POS forms.1
- Exp. No.:2 Half Adder And Full AdderTo design and realize half adder and full adder and verify the truth table using basic gates and universal gates1
- Exp. No.:3 Half Subtractor and Full SubtractorTo design and realize half subtractor and full subtractor and verify the truth table using basic gates and universal gates1
- Exp. No.:4 Multiplexer and DemultiplexerTo design and implement mux/demux and encoder/decoder using logic gates1
- Exp. No.:5 Study of Flip Flops• To study about flip flops and verify the truth tables of master slave JK, D and T flip Flop using logic gates. • Familiarize with flip flop ICs 7473 (JK flip flop), 7474 (D flip flop) and 7476 (JK flip flop).1
- Exp. No.:6 Asynchronous Counters• To design and realize 3-bit Asynchronous up counter, Asynchronous down counter and 3- bit asynchronous up-down counter. • To design and realize 4-bit up counter. • To design and realize Mod – 6 counter.1
- Exp. No.:7 Synchronous Counters• To design and construct 4-bit synchronous up counter • To design and construct 3 bit up/down counter1
- Exp. No.:8 Shift RegistersTo design and setup shift registers and to study SISO, SIPO, PIPO and PISO using IC7474.1
- Exp. No.:9 Ring Counter and Johnson CounterTo design and setup four bit Ring counter and Johnson counter using J K Flip flop1
- Exp. No.:10 Encoder and DecoderTo design and implement encoder/decoder using logic gates1
- Part B – VERILOGINTRODUCTION1
- Exp. No.:1 LOGIC GATESWrite a Verilog program for logic gates and universal gates using any type of modelling1
- Exp. No.:2 HALF ADDERWrite a Verilog program for half adder using data flow and gate level modelling1
- Exp. No.:3 FULL ADDERWrite a Verilog program for full adder using gate level modelling and behavioral level modelling.1
- Exp. No.:4 HALF SUBTRACTORWrite a verilog code for half subtractor using dataflow and structural modelling.1
- Exp. No.:5 FULL SUBTRACTORTo write a verilog code for full subtractor using behavioural level and structural level modelling.1
- Exp. No.: 6 MULTIPLEXERWrite a Verilog program for Multiplexer using gate level and dataflow modelling1
- Exp. No.:7 DEMULTIPLEXERWrite a Verilog program for De-multiplexer using gate level and dataflow modelling.1
- Exp. No.:8 ENCODERWrite a Verilog program for encoder using gate level and dataflow modelling.1
- Exp. No.:9 DECODERWrite a Verilog program for encoder using gate level and dataflow modelling.1
- Exp. No.:10 FOUR BIT FULL ADDER/PARALLEL ADDERWrite Verilog code for 4-bit full adder / parallel adder using 1 bit full adder using structural level modelling.1
- Exp. No.:11 FULL ADDER USING TWO HALF ADDERSWrite Verilog code for full adder using two half adders using structural level modelling1
- Exp. No.:12 FLIP FLOPSWrite Verilog code for the following flip flops using behavioural modelling.1. JK flip flop 2. SR flip flop 3. D flip flop 4. T flip flop1
- Exp. No.:13 EQUATION SOLVINGWrite Verilog code for the equation given below using gate level and data level modelling. 1) y = abc + a’b’c + a’b’c’ + ab’c 2) y = ab + c’ + abc1
- Exp. No.:14 SYNCHRONOUS COUNTERWrite a Verilog program for synchronous up down counter using behavioural level modelling and structural level modelling.1
- Exp. No.:15 ASYNCHRONOUS COUNTERWrite a Verilog program for asynchronous up down counter using behavioural level modelling and structural level modelling.1
- Exp. No.:16 RING COUNTERWrite a Verilog program for ring counter using structural level modelling.1
- Exp. No.:17 JOHNSON COUNTERWrite a Verilog program for Johnson counter using structural level modelling1
- VIVA QuestionsDigital Lab viva questions1
